Conventionally, decoding of bit streams which are generated by compressing digital data of pictures, sounds, and the like, has been carried out by using a decoding apparatus as shown in FIG. 56.
FIG. 56 is a block diagram illustrating a conventional decoding apparatus, and FIG. 57 is a block diagram illustrating a more specific construction for implementing the block diagram shown in FIG. 56.
In the decoding apparatus shown in FIG. 56, a system control circuit 1090 instructs a bit stream output circuit 108 to receive any broadcast, and output any bit stream in the broadcast, on the basis of a channel ID that is instructed from a user information setting circuit 1110 to the system control circuit 1090, or a channel ID that is stored in the system control circuit 1090.
In the bit stream output circuit 108, an audio bit stream and a video bit stream to be decoded by a decoding circuit 101 are output from the received broadcast, by a digital broadcast reception circuit 1081 and a data separation circuit 1082 which are shown in FIG. 57.
Initially, the digital broadcast reception circuit 1081 shown in FIG. 57 receives a broadcast to be decoded, according to an instruction from the system control circuit 1090, and performs channel decoding to output a bit stream BST. The data separation circuit 1082 separates an audio bit stream AST and a video bit stream VST to be decoded, from the bit stream BST, according to an instruction from the system control circuit 1090, and outputs the separated bit streams AST and VST.
An audio bit stream buffer 1042 and a video bit stream buffer 1041 for holding the audio bit stream AST and the video bit stream VST, respectively, which are output from the bit stream output circuit 108 are secured in a frame memory 104, and the respective stream buffers 1042 and 1041 function as FIFO memories to output the audio and video bit streams to the decoding circuit 101. In order to make the stream buffers 1042 and 1041 function as FIFO memories, management of the remaining capacities of buffers as well as input/output of streams are controlled by the bit stream output circuit 108, the frame memory 104, the decoding circuit 101, and the like.
In the decoding circuit 101, the audio bit stream and the video bit stream, which are supplied from the frame memory 104, are decoded by an audio decoding circuit 1012 and a video decoding circuit 1011, respectively, and the decoding results are output to an audio data buffer 1044 and a video data buffer 1043 which are secured in the frame memory 104, respectively. In order to assure real-time processing in the decoding circuit 101, it is necessary to complete the processing within a processing time corresponding to a unit of coded data. This will be described by taking a video decoding process as an example, with reference to FIGS. 58 and 59.
It is assumed that, in FIGS. 58 and 59, video data are coded in units of frames. Assuming that a picture of 480i, i.e., an interlaced picture of 480 scanning lines, is coded, a video decoding process VDP at this time should be completed within a frame time F (one-half of the frame time is a field time, and the frame time corresponds to twice a V period that is an interval from a video blanking to a next video blanking), and FIG. 58 shows this conception. Conversely, FIG. 59 shows a case where the video decoding process VDP is not completed within the frame time, resulting in defective pictures being outputted, such as a picture in which missing of frames has occurred during decoding, or a picture in which frames have not completely been decoded. Accordingly, in order to prevent such defective pictures from being output, a control for outputting normally decoded pictures from the decoding circuit is carried out.
In FIG. 56, the decoding circuit 101 judges which picture is to be output, and the result of the judgment is informed to a synthesis circuit 1000 through the system control circuit 1090. However, the result of the judgment may be directly informed from the decoding circuit 101 to the synthesis circuit 1000.
The decoded audio data is output from the audio data buffer 1044 to an audio/video output circuit 1100, wherein the decoded audio data is converted into an analog audio output “a” by an audio D/A conversion circuit 1101a, and converted into a digital audio output “da” by an audio data signal conversion circuit 11011a. 
Further, the system control circuit 1090 generates still pictures and on-screen displays (OSDs), and stores them in still picture regions Sti110, Sti111 (s0,s1) and on-screen display regions OSD0, OSD1 (o0,o1), respectively.
The synthesis circuit 1000 synthesizes the video data stored in the video data buffer 1043 with any of the still pictures stored in the still picture regions Sti110, Sti111 (s0, s1) and any of the on-screen display images stored in the on-screen display regions OSD0, OSD1 (o0, o1), on the basis of synthesis parameters instructed from the system control circuit 1090, to output composite video data.
The composite video data is output from the synthesis circuit 1000 to the audio/video output circuit 1100, wherein the composite video data is converted into an analog video output “v” by a video D/A conversion circuit 1101v, and converted into a digital video output “dv” by a video data signal conversion circuit 11011v. 
As described above, the decoding apparatus shown in FIG. 56 decodes a picture and a sound from a bit stream.
In the conventional decoding apparatus constructed as described above, it is premised that a picture and a sound are decoded from a bit stream. Accordingly, in order to decode plural pictures and sounds simultaneously from plural bit streams of, for example, a BS (Broadcasting Satellite) digital broadcast, a CS (Communication Satellite) digital broadcast, a 110° CS digital broadcast (a digital broadcast by a CS that is launched at 110 degrees east longitude), and the like, plural decoding apparatuses which number as many as the bit streams to be decoded are required.